august 2011 ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 nc7sz74 ? tinylogic ? uhs d-type flip-flow with preset and clear nc7sz74 tinylogic ? uhs d-type, flip-flop with preset and clear features ? ultra-high speed: t pd 2.6ns (typical) into 50pf at 5v v cc ? high output drive: 24ma at 3v v cc ? broad v cc operating range: 1.65v to 5.5v ? power down high-impedance inputs/outputs ? over-voltage tolerance inputs facilitate 5v to 3v translation ? proprietary noise/emi reduction circuitry ? ultra-small micropak? package ? space-saving us8 surface mount package description the nc7sz74 is a single, d-type, cmos flip-flop with preset and clear from fairchild?s ultra high-speed series of tinylogic ? . the device is fabricated with advanced cmos technology to achieve ultra high speed with high output drive, while maintaining low static power dissipation over a very broad v cc operating range of 1.65v to 5.5v v cc . the inputs and outputs are high impedance when v cc is 0v. inputs tolerate voltages up to 7v, independent of v cc operating voltage. the signal level applied to the d input is transferred to the q output during the positive-going transition of the clk pulse. ordering information part number top mark package packing method nc7sz74k8x sz74 8-lead us8, jedec mo-187, variation ca 3.1mm wide- 3000 units on tape & reel nc7sz74l8x n9 8-lead micropak, 1.6 mm wide 5000 units on tape & reel
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 2 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear connection diagrams ieee/iec figure 1. logic symbol pin configurations figure 2. us8 (top view) figure 3. micropak? (top through view) pin definitions pin # us8 pin # micropak name description 1 7 ck clock pulse input 2 6 d data input 3 5 /q flip-flop output 4 4 gnd ground 5 3 q flip-flop output 6 2 /clr direct clear input 7 1 /pr direct preset input 8 8 v cc supply voltage function table inputs output function /clr /pr d ck q /q l h x x l h clear h l x x h l preset l l x x h h h h l ? l h h h h ? h l h h x ? q n /q n no change h = high logic level qn = no change in data x = immaterial ??? falling edge ? l = low logic level z = high impedance ? = rising edge
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 3 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 7.0 v v in dc input voltage -0.5 7.0 v v out dc output voltage -0.5 7.0 v i ik dc input diode current v in < 0v -50 ma i ok dc output diode current v out < 0v -50 ma i out dc output source/sink current 50 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature (soldering, 10 seconds) +260 c p d power dissipation at +85c 250 mw esd human body model, jedec:jesd22-a114 5000 v charge device model: jedec:jesd22-c101 2000 recommended operating conditions the recommended operatin g conditions table defines the conditions for act ual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage operating 1.65 5.50 v supply voltage data retention 1.50 5.50 v in input voltage 0 5.5 v v out output voltage active state 0 v cc v 3-state 0 5.5 t r , t f input rise and fall times v cc =1.8v, 2.5v 0.2v 0 20 ns/v v cc =3.3v 0.3v 0 10 v cc =5.0v 0.5v 0 5 t a operating temperature -40 +85 c ? ja thermal resistance us8 250 c/w micropak?-8 280 note: 1. unused inputs must be held high or low. they may not float.
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 4 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear dc electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units min. typ. max. min. max. v ih high level control input voltage 1.65 to 1.95 0.75v cc 0.75v cc v 2.30 to 5.50 0.70v cc 0.70v cc v il low level control input voltage 1.65 to 1.95 0.25v cc 0.25v cc v 2.30 to 5.50 0.30v cc 0.30v cc v oh high level output voltage 1.65 v in =v ih , i oh =-100a 1.55 1.65 1.55 v 2.30 2.20 2.30 2.20 3.00 2.90 3.00 2.90 4.50 4.40 4.50 4.40 1.65 i oh =-4ma 1.29 1.52 1.29 2.30 i oh =-8ma 1.90 2.15 1.90 3.00 i oh =-16ma 2.40 2.80 2.40 3.00 i oh =-24ma 2.30 2.68 2.30 4.50 i oh =-32ma 3.80 4.20 3.80 v ol low level control output voltage 1.65 v in =v ih , i ol =100a 0.10 0.10 v 2.30 0.10 0.10 3.00 0.10 0.10 4.50 0.10 0.10 1.65 i ol =4ma 0.80 0.24 0.24 2.30 i ol =8ma 0.10 0.30 0.30 3.00 i ol =16ma 0.15 0.40 0.40 3.00 i ol =24ma 0.22 0.55 0.55 4.50 i ol =32ma 0.22 0.55 0.55 i in input leakage current 0 to 5.5 ??? v in ? 5.5v 0.1 1.0 a i off power off leakage current 0 v in or v out =5.5v 1 10 a i cc quiescent supply current 1.65 to 5.50 v in =5.5v, gnd 1 10 a
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 5 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear ac electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units figure min. typ. max. min. max. f max maximum clock frequency 1.80 0.15 c l =15pf r d =1m ? s 1 =open 75 75 figure 4 figure 8 2.50 0.20 150 150 3.30 0.30 200 200 5.00 0.50 250 250 3.30 0.50 c l =50pf r d =500 ? , s 1 =open 175 175 5.00 0.50 200 200 t plh , t phl propagation delay ck to q, /q 1.80 0.15 c l =15pf, r d =1m ?? s 1 =open 2.5 6.5 12.5 2.5 13.0 ns figure 4 figure 6 2.50 0.20 1.5 3.8 7.5 1.5 8.0 3.30 0.30 1.0 2.8 6.5 1.0 7.0 5.00 0.50 0.8 2.2 4.5 0.8 5.0 3.30 0.30 c l =50pf r d =500 ? , s 1 =open 1.0 3.4 7.0 1.0 7.5 5.00 0.50 1.0 2.6 5.0 1.0 5.5 t plh , t phl propagation delay /clr, /pr to q, /q 1.80 0.15 c l =15pf, r l =1m ?? s 1 =open 2.5 6.5 14.0 2.5 14.5 ns figure 4 figure 6 2.50 0.20 1.5 3.8 9.0 1.5 9.5 3.30 0.30 1.0 2.8 6.5 1.0 7.0 5.00 0.50 0.8 2.2 5.0 0.8 5.5 3.30 0.30 c l =50pf, r d =500 ??? s 1 =open 1.0 3.4 7.0 1.0 7.5 5.00 0.50 1.0 2.6 5.0 1.0 5.5 t s setup time ck to d 1.80 0.15 c l =15pf, r l =1m ?? s 1 =open 6.5 6.5 ns figure 4 figure 7 2.50 0.20 3.5 3.5 3.30 0.30 2.0 2.0 5.00 0.50 1.5 1.5 3.30 0.30 c l =50pf, r d =500 ??? s 1 =open 2.0 2.0 5.00 0.50 1.5 1.5 t h hold time, ck to d 1.80 0.15 c l =15pf, r l =1m ?? s 1 =open 0.5 0.5 ns figure 4 figure 7 2.50 0.20 0.5 0.5 3.30 0.30 0.5 0.5 5.00 0.50 0.5 0.5 3.30 0.30 c l =50pf, r d =500 ??? s 1 =open 0.5 0.5 5.00 0.50 0.5 0.5 t w pulse width, ck, /pr, /clr 1.80 0.15 c l =15pf, r l =1m ?? s 1 =open 6.0 6.0 ns figure 4 figure 8 2.50 0.20 4.0 4.0 3.30 0.30 3.0 3.0 5.00 0.50 2.0 2.0 3.30 0.30 c l =50pf, r d =500 ??? s 1 =open 3.0 3.0 5.00 0.50 2.0 2.0 t rec recover time /clr, /pr to ck 1.80 0.15 c l =15pf, r l =1m ?? s 1 =open 8.0 8.0 ns figure 4 figure 7 2.50 0.20 4.5 4.5 3.30 0.30 3.0 3.0 5.00 0.50 3.0 3.0 3.30 0.30 c l =50pf, r d =500 ??? s 1 =open 3.0 3.0 5.00 0.50 3.0 3.0 continued on the following page?
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 6 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear ac electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units figure min. typ. min. typ. min. c in input capacitance 0 3 pf c out output capacitance 0 4 pf c pd power dissipation capacitance (2) 3.30 10 pf 5.00 12 note: 2. c pd is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (i ccd ) at no output loading and operating at 50% duty cycle. c pd is related to i ccd dynamic operating current by the expression: i ccd =(c pd )(v cc )(f in )+(i cc static). note: 3. c l includes load and stray capacitance. input prr=1.0mhz t w =500ns. notes: 4. cp input=ac waveforms t r =t f =2.5ns. 5. cp input prr=10mhz; duty cycle=50%. 6. d input prr=5mhz; duty cycle=50%. figure 4. ac test circuit figure 5. i ccd test circuit figure 6. ac waveforms figure 7. ac waveforms figure 8. ac waveforms
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 7 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear physical dimensions figure 9. 8-lead us8, jedec mo -187, variation ca 3.1mm wide package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf . package designator tape section cavity number cavity status cover type status k8x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed side view top view recommended land pattern a b 0.50 seating plane 0.10-0.18 0.13 ab c 0.50 detail a 0.4 typ all lead tips 0.2 c b a pin 1 ident all lead tips 0.1 c 8 1 4 5 (8x) 0.70 2.70 3.40 1.00 detail a 1.80 gage plane 0.12 c. dimensions are exclusive of burrs, d. dimensions and tolerances per mold flash, and tie bar extrusions. b. dimensions are in millimeters. a. conforms to jedec registration mo-187 ansi y14.5m, 1994. 2.10 1.90 2.40 2.20 0.15 3.20 3.00 1.55 0.90 max 0.10 0.00 0.80 0.60 0.17-0.27 (8x) 0.30 (8x) 0.20-0.35 0-8 c seating plane e. file drawing name : mkt-mab08arev4
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 8 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear physical dimensions figure 10. 8-lead, micropak?, 1.6mm wide package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l8x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed (0.09) (0.1) (0.2) 1.6 2x 0.05 0.00 1.6 2x c 0.05 c 4 3. drawing conforms to asme y.14m-1994 2. dimensions are in millimeters 1. package conforms to jedec mo-255 variation uaad bottom view 4. pin 1 flag, end of package offset mac08arev4 1 23 5 6 7 8 notes: 8x 0.25 0.35 3x 8x 1.0 4 0.5 8x 0.25 0.15 0.10 cab 0.05 c 0.10 c top view index area b recommended landpattern a 0.10 c 0.55 max 0.05 c detail a 0.35 0.25 (0.15) (0.20) 0.35 0.25 detail a pin #1 terminal scale: 2x 5. drawing file name: mkt-mac08arev4
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sz74 ? rev. 1.0.2 9 nc7sz74 ? tinylogic ? uhs d-type flip-flop with preset and clear
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